최재혁 교수 연구실

Integrated Circuits & Systems Lab

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최재혁 교수

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A Low-Jitter Fractional-N Sampling PLL with Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication TechniqueIEEE Journal of Solid-State Circuits (JSSC), Early Access · 2026
A 16.8-33.6Gb/s, 0.93pJ/b Direct-Frequency-Tracking Digital CDR with an SSC Profile Replicator for Per-Lane Data-Rate Variation and High Jitter Tolerance under Deep SSCIEEE Symp. VLSI Circuits · 2026
A Versatile On-Chip Jitter Measurement Circuit with Dynamic Quantizer-Resolution Adaptation for Arbitrary Clocks across 1-8GHz and 20-130pspp JitterIEEE Symp. VLSI Circuits · 2026
An 85.5-to-94.5-GHz W-Band Fully-Symmetric Quadrature LO Generator with a Fast Quadrature Calibration TechniqueIEEE RFIC Symposium · 2026
A Comprehensive Power-Supply-Induced Jitter Mitigation Scheme for HBM Interfaces Using a Strobe-Triggered Digital LDO and Local Replica RegulatorsIEEE Custom Integrated Circuits Conference (CICC) · 2026
A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-based LMS CalibrationIEEE Journal of Solid-State Circuits (JSSC) · 2025