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Younghyun Lim

Younghyun Lim

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학부·대학원 연구생 상시 모집(석박사통합 권장).

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Professor

About

임영현 교수 연구실(ACHIEVE Lab)은 경희대 전자공학과 소속으로, 아날로그/RF 집적회로를 연구한다. 5G 트랜시버용 RF/아날로그 회로와 IoT용 저전력·소형 RF/아날로그 회로 설계를 다룬다.

Research keywords

아날로그/RF 집적회로 설계 (PLLLDO송수신기 등) — Analog RF Circuits Lab (ARCL)

Selected publications

  • A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM InterfacesIEEE Journal of Solid-State Circuits (JSSC), Early Access · 2025
  • An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail InductorsIEEE Transactions on Circuits and Systems II: Express Briefs · 2025
  • A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error CancellationIEEE Journal of Solid-State Circuits (JSSC) · 2024
  • A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency MultiplierIEEE Journal of Solid-State Circuits (JSSC) · 2023
  • A Wide-Lock-In-Range and Low-Jitter 12-14.5-GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting LoopIEEE Journal of Solid-State Circuits (JSSC) · 2022
  • A 170MHz-Lock-In-Range and -253dB-FOMjitter, 12-14.5GHz Subsampling PLL with a 150uW Frequency-Disturbance-Correcting LoopIEEE International Solid-State Circuits Conference (ISSCC) · 2020

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