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Jungsoo Lee

Jungsoo Lee

POSTECH · Electrical Engineering

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Professor

Prof. 이정수

Professor's page · publications

About

나노소자 및 공정 연구실은 반도체 나노소자의 설계와 제작 공정을 연구한다. 차세대 트랜지스터 구조, 박막 공정, 소자 신뢰성 등 나노스케일 전자소자 기술을 통해 더 작고 빠른 반도체 구현을 추구한다.

Research keywords

나노소자 및 공정 연구실

Selected publications

  • Influence of CF4 and SF6 Plasma-Induced Surface Chemistry on Barrier Height and Contact Resistivity of Ti/Al Contacts to p-Type 4H-SiCMaterials Science in Semiconductor Processing · 2026
  • Hole Trap Extraction in Charge Trap Layer of 3D NAND Flash MemoryIEEE Transactions on Electron Devices · 2026
  • Highly Sensitive Si-Based Electrolyte-Gated Transistor Array for Multiplexed Detection of ArbovirusesMicromachines · 2025
  • Highly Enhanced Sensing Performances of Si-based Electrolyte-Gated Transistor (EGT) Using Silver Nanowire Coating Method in Chikungunya DetectionIEEE Sensors Journal · 2025
  • Analysis of Charge Loss Decomposition and Nonlinear Ea in 3-D NAND Flash Memory Using a Neutral Cell-Based MethodIEEE Electron Device Letters · 2025
  • Impact of Electron and Hole Trap Profiles in BE-TOX on Retention Characteristics of 3D NAND Flash MemoryIEEE Transactions on Nanotechnology · 2024

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